Problems





Problems

1.

If a bug is detected while running a simulation under a revision control system, the environment variables required to reproduce the bug must include the versions of all the files used in the simulation.

  1. List three revision control software programs, whether public domain or commercial.

  2. Select one revision control software program from the previous answer. What are the commands to capture the view of the simulation?

  3. (Optional) Write a script that saves a view to file view.sv. Write another script to restore the view from view.sv.

2.

To reduce circuit scope in debugging, it is often necessary to carve out a block of the circuit from a full chip and focus debugging on that block. To do so, a test bench modelling the surrounding circuit around the block has to be created. The test bench instantiates the block and drives the inputs of the block with the waveforms of the inputs captured in a full chip simulation run.

  1. Construct a test bench for the following block. Assume that captured waveforms for the inputs are shown in Figure and the block has the following interface:

    module buggy_block (in1, in2, in3, out1, out2, out3)
    input [31:0] in1;
    input [3:0] in2;
    input in3;
    output [31:0] out1;
    output out2, out3;
    

    18. Captured input waveforms for block test bench


  2. Suppose input in3 is an I/O port. What difficulty may arise from your test bench? How could such a difficulty be dealt with?

3.

In practice, midpoint statements in a test case are often approximated for various reasons. For example, the exact midpoint is difficult to compute or the state at the exact midpoint statement is complicated. Besides, if an approximation yields only a few more lines of statements while making restarting much easier, it is well worthwhile. In this exercise, assume that a microprocessor runs a C program shown in Figure and an error occurs. Furthermore, let's assume the inner loop, L3, is indivisible, meaning if an approximation for a midpoint statement is to be used, it should not happen inside L3. Use a binary test case reduction algorithm to trim down the test case. For simplicity, assume all assignment statements are of equal weight.

  1. Formulate an equation to find a midpoint statement of the code. If you are to solve the equation, do you expect the value from the equation to be an integer?

  2. To simulate from the midpoint statement found in the previous answer, what variables must be saved to enable restarting from the midpoint statement?

  3. (Optional) If loop L3 is not indivisible, formulate the midpoint statement equation.

    19. A C program test case for a bisection search


4.

Let's consider the optimal check pointing interval. In a design, the average number of simulation cycles from the time an error is triggered to the time it is observed is P. Assume an error can occur at any cycle with equal probability, and simulations are run with a check pointing interval of L (in other words, the design is check pointed every L cycles).

  1. Define the debug interval of an error to be the number of cycles from the last check point at which the error was triggered to the time it is observed. Show that the mean debug interval can be expressed as shown here, where E is the expectation operator on variable t over interval [0, L], and t is the time of error occurrence modulo L. Assume P is greater than or equal to L:


  2. What should DI be if P is less than L?

  3. Assume P is at least L and that the cost associated with simulating a cycle in the debug interval is ten and the cost of generating a check point at interval L is 15/L. The total cost of debugging consists of the cost of generating the check points up to the point an error is observed plus the cost of simulating the debug interval during debugging. Derive a total debug cost function. For P = 5, find an optimal L that minimizes the total debug cost.

5.

Referring to the five states of issue tracking, describe the roles of the manager and engineers, and the transitions of the states in each of the following scenarios.

  1. A bug was filed because of a user error.

  2. A bug cannot be reproduced because by the time it got to an engineer, the design was already improved not to produce the bug.

  3. A bug is about inconsistency between design and its documentation.

  4. A bug cannot be reproduced, possibly an intermittent bug.

  5. A bug is another manifestation of another bug being worked.

6.

For the circuit in Figure, construct a forward tracing branching diagram with a depth of 3. The error site is X. Repeat for backward tracing.

20. Circuit for creating branching diagrams


7.

Derive a two-cycle fanin cone for node X in the circuit shown in Figure.

21. Circuit for fanin cone unrolling


8.

Consider the circuit and clock waveforms shown in Figure.

  1. If the current time is just before 100, when is last clock edge before time 100 that may cause a transition at node X?

  2. Show by tracing signals that both inputs of the multiplexor being 0 cannot be a steady state. A steady state has settled in the clock cycle.

  3. Show that in1=0 and select=1 cannot be a steady state.

  4. Show that in0=0 and select=0 can be a steady state.

    22. Circuit for driver and load tracing


9.

Consider the following RTL code. If message "error found" is displayed, how do you go about finding the root cause using the backward tracing method? What problem may be encountered during your debugging process?

   always @(posedge clk) begin
      hit = 1'b0;
      for(i=0; i<=10; i=i+1) begin
         vt = target[i];
         if(vt == checked) hit = 1'b1;
      end
   end

   always @(negedge clk)
   if (hit == 1'b1) $display ("error found");

10.

In this problem, you learn to check point and restore from a check point, and dump out signals to debug. The following code is an asynchronous queue. First get familiar with the code and the functionality of the queue:

   module top;
      parameter WIDTH = 32;
      reg [WIDTH-1:0] in;
      wire [WIDTH-1:0] out;
      wire full, empty;
      reg enq, deq, reset;

      initial begin
         enq=1'b0;
         deq=1'b0;
         reset <= 1'b1;
        // add your input stimuli below
      end

      queue m(.in(in), .out(out), .enq(enq), .deq(deq),
   .full(full), .empty(empty), .reset(reset));
   endmodule

   module queue(
      out,      // queue head
      full,     // 1 if FIFO is full
      empty,    // 1 if FIFO is empty
      reset,    // reset queue
      in,       // input data
      enq,      // enqueue an input
      deq      // dequeue the head of queue
   );

      parameter WIDTH = 32; // queue width parameter
      DEPTH = 3; // length of queue

      output [(WIDTH-1):0] out;
      output full, empty;
      reg full, empty;
      input reset, enq, deq;
      input [(WIDTH-1):0] in;
      integer ic; // item count
      integer i; // index

      reg [(WIDTH-1):0] item [0: (DEPTH-1)]; // queue

   // output is the head of the queue
   assign out = item[0];

   always @(posedge reset)
      begin // reset queue
         ic = 0;
         full <= 1'b0;
         empty <= 1'b1;
      end

   always @(posedge enq or posedge deq)
      begin // enqueue or dequeue
      case ({enq, deq})
        2'b00: ;
        2'b01: // dequeue head of queue
         begin
            for (i=1; i<ic; i=i+1)
               item[i-1] <= item[i];
            ic = ic-1;
         end
         2'b10: // enqueue input item
         begin
            item[ic] <= in;
            ic = ic+1;
         end
         2'b11: // enqueue and dequeue simultaneously
         begin
            for (i=1; i<ic; i=i+1)
               item[i-1] <= item[i];
            item[ic-1] <= in;
         end
       endcase

       full <= (ic == DEPTH) ? 1'b1 : 1'b0;
       empty <= (ic == 0) ? 1'b1 : 1'b0;
       end // always

    endmodule

  1. Add stimuli to the initial block so that the three items 32'h12345678, 32'h90abcdef, and 32'hfeedbeef are added to the queue at times 20, 40, and 60 respectively. Then dequeue them at times 100, 120, and 140 respectively. Simulate the design to demonstrate that your stimuli indeed enqueue and dequeue as expected by printing out the queue contents at those times.

  2. Check point the circuit at time 80 and exit the simulator. Then, restart the simulation using the check point. Show that the three items are dequeued as expected.

  3. Restart a simulation from the second-to-last check point and dump out all nodes in VCD format.

11.

Use the following stimuli to simulate the asynchronous queue in the previous problem:

   enq <= 1'b0;
   deq <= 1'b0;
   reset <= 1'b1;
   #5 reset <= 1'b0;
   #5 in = 32'habcdef;
   enq <= 1'b1;
   #5 enq <= 1'b0;
   #5 deq <= 1'b1;
   #5 deq <= 1'b0;
   #5 deq <= 1'b1;
   #5 deq <= 1'b0;
   #5 in = 32'h12345;
   enq <= 1'b1;
   #5 enq <= 1'b0;
   #5 in = 32'hbeef;
   enq <= 1'b1;
   #5 enq <= 1'b0;
   #5 deq <= 1'b0;
   #5 deq <= 1'b1;
   #5 deq <= 1'b0;

  1. What operations do these vectors perform? Does the queue function as expected? If not, dump out all nodes in VCD format and use a debugger to determine the root cause.

  2. Fix the bug and rerun the simulation to confirm.

  3. What debugger did you use? Were you able to dump out the contents of an array item? Was the debugger able to annotate the contents of the array item to RTL?

12.

For each of the following tasks, decide whether a branch in a revision system should be created to accomplish the task for the files in question.

  1. Fix a bug in the FPU in a CPU design project.

  2. Create a model for hardware acceleration on top of the synthesis model.

  3. Based on the RTL model, create an algorithmic model for a formal verification tool.

  4. Add postsilicon debugging facilities to an RTL model.

13.

Consider the plots of bug rate, coverage, and simulation cycles in Figure.

  1. Plot A displays bug rate versus coverage. Give an explanation for the behavior of the coverage metric in the shaded region.

  2. Plot B shows bug rate versus simulation cycles. Is it possible for the bug rate to have a "hump" as shown in the shaded area? Give a possible scenario for the hump.

  3. What can you say about the test vectors and the coverage metric in the shaded area of plot C?

    23. Interpretations of bug rate, coverage, and simulation cycles


14.

A computing resource for a project is usually tiered in terms of response time and computing capacity, such as performance, memory, and disk space. Three tiers are possible: computer farm, project server, and engineer's workstation. A computer farm is shared with other projects and jobs are queued, and it usually has the largest capacity among the three. Large jobs that do not require fast turnaround times are sent to a computer farm. Project servers are used for running large jobs from the project that need a response faster than that given by a computer farm. An engineer's workstation is reserved for the quickest response and small computing jobs. For each of following tasks, decide to which computing resource to send the task.

  1. Run a check-in test to verify a bug fix is correct

  2. Debug a unit

  3. Run a nightly regression

  4. Run a major release regression

  5. Check in a file


     Python   SQL   Java   php   Perl 
     game development   web development   internet   *nix   graphics   hardware 
     telecommunications   C++ 
     Flash   Active Directory   Windows