In this chapter we first illustrated the interplay among the three verification entities: test plan, assertion, and coverage, and how they contribute to design controllability and observability, and enumerating test corner cases. Next, three levels of hierarchical verification were presented as a way to handle large designs. We then studied test plan generation, which consists of extracting functionality from architectural specifications, prioritizing functionality, creating test cases, and tracking progress. In particular, we used a state space method as a guide to enumerate corner cases systematically. As a complement to directed test generation, we studied the structure of pseudorandom test generators by focusing on a generic random code generator. The next major section emphasized assertion. First, the four components of an assertion were illustrated. Then, common assertion classes were discussed in two categories: combinational and sequential assertions. In combinational assertions we discussed checking for signal range, unknown value, parity, signal membership, and one-hot/cold-ness. In sequential assertions we covered assertions on time window, interval constraint, and unclocked timing requirements, and concluded with container assertion. We then looked at SystemVerilog assertions and discussed sequence construction and operators, along with built-in system functions. In the final major section, we studied verification coverage in three stages: code coverage, parameter coverage, and functional coverage. We illustrated each type of coverage and compared their advantages and disadvantages.