April 6, 2011, 1:15 p.m.
posted by nfrank
Two-State and Four-State Simulation
Four-state (0, 1, x, and z) simulation has been in common use to detect design problems such as uninitialized states and bus contention in which the states and the bus are assigned x value. Value x denotes an unknown value and value z denotes high impedance. A simulator is a four-state simulator if every node can have a four-state value. A two-state simulator uses only 0 and 1 values. A two-state simulator is faster than a four-state simulator. If a node is uninitialized or a bus is in high impedance or contention, a two-state simulator maps x and z to either 0 or 1. It is common practice to simulate a design using a four-state simulator during the power-up stage until most nodes are initialized, then the design is switched to a two-state simulator for faster speed.
Because a real circuit does not compare or operate with x or z values, the design should never have x or z values (except for the case when x, z, and ? are used for synthesis purpose, which should be used with caution because this will give rise to discrepancies between a simulation model and a synthesis model); however, a test bench can have these values. A designer should take into consideration that the design along with the test bench may undergo two-state simulation as well as four-state simulation, and hence make an effort to minimize simulation result in discrepancies between the two. Some differences are inevitable, because of the inherent pessimism of x. Consider the two-to-one multiplexor with inputs that are both 1, but select x, as shown in Figure. The algebra of unknown x is that the complement of x is also x. Therefore, the inputs to the OR gate are both x, instead of x and , producing an unknown x for the multiplexor output. This is the result of a four-state simulation. However, in reality, because both inputs of the multiplexor are 1, the output should be 1 regardless of the select value.
14. Pessimism of four-state simulation
If this multiplexor is simulated using a two-state simulator, the output will be 1, because the select value is mapped to 0.
Although inherent differences between four-state and two-state simulation exist, the designer should not allow these differences to propagate to create functional errors. Let us consider the following example:
if( FlipFlopOutput == 1'b0 ) begin count = count + 1; end
Variable FlipFlopOutput, if uninitialized at power-up, takes on value x and thus makes the comparison false. In Verilog, a conditional expression is, by default, x if any one argument is x. Therefore, variable count does not increment. On the other hand, a two-state simulator represents an uninitialized variable with value 0, and hence satisfies the condition and increments variable count by one. Consequently, the values of count differ by at least one in two-state simulation and four-state simulation, and this difference can further penetrate into other parts of the design. This type of functional difference can be hard to debug and can be quite misleading.
The proper thing to do for this type of situation is to determine whether the inputs to the block (for example, FlipFlopOutput) should be initialized. If yes, make sure they are initialized; otherwise, closely examine your block to see how it should behave in reality, when the inputs can be either 0 or 1. Does it produce different results and propagate them to create different system states? If so, the designer needs to improve the design to be better immune to uninitialized states. Similar caution should be exercised about using strength.